1. Field of Invention
This invention relates to high density integrated circuits which employ single interconnect structure for different active devices. More particularly, this invention relates to such a structure for complementary MOS integrated circuits.
2. Description of Prior Art
As the packing density of integrated circuits is improved, greater alignment accuracy is required for the devices in the circuit to prevent shorting out between such devices. This in turn requires smaller tolerances in the masks employed in the various steps in the fabricating of such devices as well as in the alignment of such masks. This is particularly true when the circuits being fabricated include complementary MOS circuits.
Complementary MOS circuits are normally circuits which employ both N channel devices and P channel devices in the same integrated circuit chip. N channel devices provide faster switching time but have higher power dissipation than P channel devices. However, these devices switch to the on condition for different polarities of the input signal. Therefore, the complementary design technique uses both P and N channel devices in tandem in a typical inverter circuit so that the inverter consumes power only when it switches. When transferring signals from one integrated circuit chip to another, the output drivers of the first chip must provide large impulses to the next chip being driven. It is important that such power is only consumed during switching, so that there is less continuous power dissipation by the output drivers.
A particular fabrication technique that allows for a reduction in process and masking steps is the employment of ion implantation. Ion implantation allows for controlled impurity doses and more shallow and smaller regions to be created in the semiconductor substrate. The extensive use of ion implantation requires a less number of thermal processing steps for impurity doping as well as reduction in the use of wet chemicals and toxic gases. Furthermore, many steps in the fabrication of a semiconductor device by diffusion must be performed in sequence so as to arrive at the desired final structure of the respective devices. However, ion implantation often allows for the order of various steps to be interchanged since the depth of the ion implantation is determined by the energy of the respective ions as they strike the target surface. Ion implantation is particularly adapted for the fabrication of an integrated circuit having a plurality of different device structures.
A prior art example of a method of forming an integrated circuit having a plurality of the different devices in it is the Shappir U.S. Pat. No. 3,921,283. However, the method of Shappir must employ a number of different masks which creates an alignment problem.
In order to place a number of different devices on an integrated circuit chip, it is necessary to be able to control a number of different device thresholds and to be able to make any device an enhancement mode device or depletion mode device. Also, the threshold can be left to be controlled by the bulk resistivity of the substrate. Enhancement mode devices are ones which are normally off if no electrical signal is supplied to their gates while depletion mode devices are normally on if no electrical signal is supplied to their gates. In addition, it is desirable to have devices that are on the brink of the threshold where the voltage in either direction turns them on or off. Still another class of devices are called weak depletion devices, which are only nominally conducting. So it is desirable to have four different types of thresholds for internal devices as well as having complementary devices. Again, prior art methods require an extra number of masking steps to form the respective devices with the consequential alignment problems which reduced the resolution with which the devices could be created and the resulting packing density.
It is then an object of the present invention to provide an improved integrated circuit chip having a plurality of different devices.
It is still another object of the present invention to provide an improved integrated circuit chip which require a minimum number of masking steps.
It is still a further object of the present invention to provide an improved integrated circuit chip which employs a single interconnect structure for different active devices on the chip.